This application claims benefit of priority under 35USC xc2xa7119 to Japanese Patent Application No. 2000-153660 filed on May 24, 2000 in Japan and Japanese Patent Application No. 2001-149496 filed on May 18, 2001 in Japan, the entire contents of which are incorporated by reference herein.
The present invention relates to a potential detector to detect an electric potential output from a high voltage generator, etc., that has reached a certain level in a semiconductor integrated circuit.
FIG. 1 shows a known potential detector 90. The detector 90 consists of resistors R1 and R2 connected in series between a terminal 91 to be detected and a ground terminal Vss, and a comparator CMP to compare a potential at a node at which the resistors R1 and R2 are connected together with a reference potential Vref.
The potential at the node of the resistors R1 and R2 is obtained as V1xc2x7R2/(R1+R2) where V1 is a potential at the terminal 91. The comparator CMP outputs a high-level detection signal when the potential at the node exceeds the reference potential Vref.
The potential detector 90 is used, for example, for detecting an output potential Vout of a high voltage generator used in a semiconductor circuit such as a non-volatile semiconductor memory.
FIG. 2 shows an example where the potential detector 90 is used for detecting a potential Vout appearing at an output terminal 91 of a high voltage generator 910 such as a charge pump. The high voltage generator 901 is driven by clocks generated by an oscillator 902 such as a ring oscillator.
The potential detector 90 outputs a detection signal Dout when the potential Vout appearing at the output terminal 91 of the high voltage generator 901 reaches a certain potential to dis-activate a gate 903 that has fed clocks generated by the oscillator 902 to the high voltage generator 901. The high voltage generator 901 then stops, so that the boosted output Vout is kept at a constant level, as illustrated in FIG. 3A.
The known potential detector generates a potential by the series-connected resistors, which is compared with a reference potential. A current always flows through the resistors R1 and R2 for generating the potential. The high voltage generator 901 thus requires a drive performance high enough for accepting a current consumed by the resistors R1 and R2. The drive performance of the high voltage generator is decided according to the resistance of the resistors R1 and R2 when a load capacitance to be driven by the high voltage generator is relatively small. This requires drive performance for the high voltage generator higher than that for the high voltage generator to drive the load itself, which is not practical in view of power consumption and circuit integration.
A high voltage generator having unnecessarily high drive performance will generate a potential boosted to a high level during a response time of a potential detector. This results in a large variation in boosted output Vout against an anticipated level, as illustrated in FIG. 3B, with difficulty in obtaining a constantly boosted potential.
The larger the resistance of the resistors R1 and R2 for avoiding such potential variation, the larger the parasitic capacitance to the resistors. This results in a large delay of change in output potential of the high voltage generator, and further a large delay time required for the output potential to be transferred to the input terminal of the comparator CMP. Change in output potential of the high voltage generator illustrated in FIG. 3C does not have an abrupt potential increase such as shown in FIG. 3B, however, exhibits a slow response. This also results in unstably un-converted potential output.
A purpose of the present invention is to provide a potential detector integrated on a small area and capable of stable potential detection while consuming a small power.
Another purpose of the present invention is to provide a semiconductor integrated circuit with the potential detector and having a high voltage generator for generating a constant potential output.
The present invention provides a potential detector comprising: a first capacitor, one terminal thereof being connected to a potential detection terminal via a first switching device, another terminal thereof being connected to a reference potential terminal; a second capacitor, a terminal thereof being connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, another terminal thereof being connected to the reference potential terminal; a third switch connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal; a clock generator for generating clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices; and a comparator for comparing a potential at the second node with a reference potential and outputting a detection signal when a potential at the potential detection terminal reaches a predetermined potential.
Moreover, the present invention provides a semiconductor integrated circuit having a high voltage generator for generating a boosted internal power supply potential and a potential detector for controlling the high voltage generator by detecting a potential at an output terminal of the high voltage generator, the potential detector comprising: a first capacitor, one terminal thereof being connected to an output terminal of the high voltage generator via a first switching device, another terminal thereof being connected to a reference potential terminal; a second capacitor, one terminal thereof being connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, another terminal thereof being connected to the reference potential terminal; a third switching device connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal; a clock generator for generating clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switching device periodically in an opposite timing for the first and the third switching devices; and a comparator for comparing a potential at the second node with a reference potential and outputting a detection signal when a potential at the potential detection terminal reaches a predetermined potential.
Furthermore, the present invention provides a semiconductor integrated circuit having a high voltage generator for generating a boosted internal power supply potential, the high voltage generator comprising: a plurality of charging circuits, each having a capacitor, one terminal thereof being connected to a high-level side power terminal via a first switching device, another terminal thereof being connected to a low-level side power terminal via a second switching device; and a plurality of third switching devices each provided between adjacent two charging circuits so that a node at which the first switching device and the capacitor of each charging circuit are connected is connected to another node at which the second switching device and the capacitor of the succeeding charging circuit are connected, wherein the capacitor of each charging circuit is charged with a potential almost equal to a power supply potential when the first and the second switching devices are turned on whereas the third switching devices are turned off and the charged capacitors of the charging circuits are coupled in series when the first and the second switching devices are turned off whereas the third switching devices are turned on, thus outputting a boosted potential.
Moreover, the present invention provides a semiconductor integrated circuit having a high voltage generator for generating a boosted internal power supply potential, the high voltage generator comprising: a charge pump having a plurality of first capacitors, adjacent two first capacitors being driven by clocks in opposite timing and a transfer device for transferring charges stored in each first capacitor to the succeeding first capacitor; and a potential converter for supplying a boosted clock to each first capacitor, wherein the potential converter includes: a second capacitor, a first terminal thereof being connected to a high-level side power terminal via a first switching device, a second terminal thereof being connected to a low-level side power terminal via a second switching device that is turned on simultaneously with the first switching device; a third switching device that is turned on in opposite timing for the first and the second switching devices to supply a driving potential to the second terminal of the second capacitor; a fourth switching device that is turned on simultaneously with the third switching device to connect the first terminal of the second capacitor to an output terminal; and a fifth switching device that is turned on simultaneously with the first switching device to reset a potential at the output terminal, wherein the second capacitor is charged while the first and the second switching devices are on and the charged second capacitor is coupled to the first capacitor in series while the third and the fourth switching devices are on.
Furthermore, the present invention provides a semiconductor integrated circuit having a high voltage generator for generating a boosted internal power supply potential, the high voltage generator comprising: a plurality of first capacitors that are charged during a first period; a plurality of second capacitors provided alternately with the first capacitors, the second capacitors being charged during a second period that partially overlaps with the first period; a first transfer device for transferring charges stored in each first capacitor to the succeeding second capacitor during a third period that is delayed from the second period by a predetermined time; and a second transfer device for transferring charges stored in each second capacitor to the succeeding first capacitor during a fourth period that is delayed from the first period by the predetermined time.